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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
September 2009
FAN6210
Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Features
Primary-Side Trigger Controller for Dual Forward Converters with Synchronous Rectifier (SR) Specialized SR Controller for Dual Forward Converter Programmable Turn-on Delay Time for the Powering SR (RDLY Pin) Winding Voltage Detection for Precision Control at Light-Load Condition (DET Pin) Green-Mode Operation to Improve Light-Load Efficiency Differential Mode Control Signal with Better Noise Immunity VDD Over-Voltage Protection (OVP)
Description
FAN6210 is a primary-side trigger Integrated Circuit (IC) specially designed for the synchronous rectifier (SR) in dual forward converters employing FSR660/630. FAN6210 provides drive signal for the primary-side power switches by using an output signal from PWM controller. FAN6210 can be combined with any PWM controller that can drive a dual-forward converter. To obtain optimal timing for the SR drive signals, transformer winding voltage is also monitored. To improve light-load efficiency, green mode operation is employed, which disables the SR turn-on trigger signal, minimizing gate drive power consumption at light load. FAN6210 is available in 8-pin SOP package.
Applications
Personal Computer (PC) Power Supply Entry-Level Server Power Supply
Ordering Information
Part Number
FAN6210MY
Operating Temperature Range
-40C to +105C
Eco Status
Green
Package
8-Pin Small Outline Package (SOP)
Packing Method
Tape & Reel
For Fairchild's definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Rising/Falling Delay
SIN
3
Green Mode (D<10%)
300ns
100ns
7 SOUT
Controlled Rising Delay
8 GND GM
GM RDLY 4
Rising Delay One-shot Vibrator
700ns
1
XP
2/3V
+
DET 5
OVP +
50ns
One-shot Vibrator Rising/Falling Delay
300ns 50ns 50ns
25.5V
One-shot Vibrator
2 XN
VDD 6 10/8V
+
300ns
Internal Bias
Figure 2. Functional Block Diagram
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Marking Information
F: Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Package Type T: M=SOP P: Y: Green Package M: Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
XN XP SIN RDLY DET VDD SOUT GND
Description
Pulse signal output terminal for SR off control signal. Pulse signal output terminal for SR on control signal. Input signal for high- and low-side gate driver outputs. Delay time setting. This delay time is SOUT rising to trigger XP pulse delay time. Sensing freewheel diode voltage. The power supply pin. Gate driving to high- and low-side gate driver. Ground.
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VSIN VSOUT VH VL PD JA TJ TSTG TL ESD DC Supply Voltage
Parameter
Logic Input Voltage Low Side Output Voltage XP, XN DET, RDLY Power Dissipation TA < 50C Thermal Dissipation (Junction to Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering) 10 seconds Human Body Model, JEDEC:JESD22-A114 Charged Device Model, JEDEC:JESD22-C101
Min.
Max.
30 30 18 30 7 400 150
Unit
V V V V V mW C/W C C C KV KV
-40 -55
+125 +150 260 4.0 1.5
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Max.
+105
Unit
C
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Electrical Characteristics
VDD=20V, TA=25, unless otherwise specified.
Symbol
VDD Section VDD VDD-ON VTH-OFF VDD-OVP VDD-OVP-HYS tOVP SIN Section VSIN tDLY_OUTH tDLY_OUTL tON_MAX DET Section VDET_H VDET_L tPD_DET tPLS_XN tPLS_XP tPD_XN DPLS_OFF VXN VXP tR_XP
Parameter
DC Supply Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage VDD Over-Voltage Protection (OVP) Hysteresis voltage for VDD OVP VDD OVP Debounce Time Logic Input Voltage Delay Time Between SIN-HIGH and SOUT-HIGH Delay Time Between SIN-LOW and SOUT-LOW SOUT Maximum On Time and Stop XP Pulse Detect Input Voltage to Send XP After SOUT Falling Voltage to Drive XP Signal After SOUT Falling Delay Time to Send XP High-Level Pulsewidth of XN Signal High-Level Pulsewidth of XP Signal
Conditions
Min. Typ. Max. Units
7 9 7 23.0 0.3 10 8 25.5 0.8 250 10.5 240 75 8.5 2.5 1.5 30 250 600 25 5.5 5.5 300 100 10.0 3.0 2.0 50 300 700 50 10 8.0 8.0 30 24.5 350 150 12.0 3.5 2.5 100 350 800 75 24 11 9 28.0 1.3 V V V V V s V ns ns s V V ns ns ns ns % V V ns
XP XN Section
Delay Time to Trigger XN by SIN Rising or Falling Edge SIN Duty Ratio Shorter than DPLS_OFF Stop XP Pulse XN Signal Output Voltage Level XP Signal Output Voltage Level XP Rising Time VDD = 15V; CL = 100pF; SOUT= 1V to 6V VDD = 15V; CL = 100pF; SOUT= 7V to 2V RRDLY=24k RRDLY=24k VDD=25V VDD=15V; IO = 50mA VDD=15V; IO = 50mA VDD = 15V; CL = 5nF; SOUT= 2V to 9V VDD = 15V; CL = 5nF; SOUT= 9V to 2V
tF_XP
XP Falling Time
30
ns
RDLY Section VRDLY tDLY_XP VZ VOL VOH tR tF RDLY Voltage Delay Time to Trigger XP by SOUT Rising Edge Output Voltage Maximum (Clamp) Output Voltage LOW Output Voltage HIGH SOUT Rising Time SOUT Falling Time 1.08 280 1.20 340 1.32 400 18.5 1.5 10 30 30 70 50 120 100 V ns V V V ns ns
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Typical Performance Characteristics
These characteristic graphs are normalized at TA = 25C.
11.0
9.00
10.5
8.75
VTH -OFF (V)
V DD-ON (V)
10.0
8.50
9.5
8.25
9.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
8.00 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 5. Turn-On Threshold Voltage
Figure 6. Turn-Off Threshold Voltage
350
150 140
tDLY_OUTH (ns)
tDLY_OUTL (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
330
130 120 110 100 -40 -25 -10 5 20 35 50 65 80 95 110 125
310
290
270
Temperature
Temperature
Figure 7. Delay Time Between SIN-HIGH and SOUT-HIGH
Figure 8. Delay Time Between SIN-LOW and SOUT-LOW
340
740
320
720
tP LS _XN (ns)
300
tP LS _XP (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
700
280
680
260
660 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 9. High-Level Pulsewidth of XN Signal
Figure 10. High-Level Pulsewidth of XP Signal
70
400 380
60
360
tP LS _XP (ns)
-40 -25 -10 5 20 35 50 65 80 95 110 125
tP D_XN (ns)
340 320 300 280 260
50
40
30
240 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature
Temperature
Figure 11. Delay Time to Trigger XN by SIN Rising or Falling Edge
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
Figure 12. Delay Time to Trigger XP by SOUT Rising Edge
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Function Description
Figure 13 and Figure 14 show the simplified circuit diagram of dual-forward converter and its key waveforms. Switches Q1 and Q2 are turned on and off together. Once Q1 and Q2 are turned on, input voltage is applied across the transformer primary side and power is delivered to the secondary side through the transformer, powering diode D1. During this time, the magnetizing current linearly increases. When Q1 and Q2 are turned off, the magnetizing current of the transformer forces the reset diodes (DR1 and DR2) and negative input voltage is applied across the transformer primary side. During this time, magnetizing current linearly decreases to zero and the secondary-side inductor current freewheels through diode D2. When synchronous rectifiers SR1 and SR2 are used instead of diodes D1 and D2, it is important to have proper timing between drive signals for SR1 and SR2. Figure 15 shows the typical application circuit of FAN6210. SIN is the gate drive output of the PWM controller. SOUT is obtained from SIN by adding a delay, which is used to drive two switches Q1 and Q2. The value of the DET resistor is recommended as 10k and DB is used to block high voltage on winding. The breakdown voltage of Zener diode DZ is typically 5~6V to protect the DET pin from over voltage.
VIN +
Q1
From PWM controller FAN6210 1 2 3 XP XN SIN GND SOUT VDD 8 7 6 5 Dz Drv DB
Drv
Q1
DR2 Lm + + Vx Im D1 SR1 Q2 SR2 D2 L IL Vo
4
RDLY DET
Q2
VIN
VD -
DR1
SN of FSR660/630 SP of FSR660/630
Figure 13. Simplified Circuit Diagram of Dual-Forward Converter
Figure 15. Typical Application Circuit Figure 16 shows the timing diagrams for heavy-load and light-load conditions. The switching operation of the secondary SR MOSFETs is determined by the SN and SP signals. FSR660/630 turns on SR MOSFETs at the rising edge of the XP signal, while it turns off SR MOSFETs at the rising edge of XN. Within one switching cycle, XP and XN are obtained two times, respectively. The XN signal has a 300ns pulse-width and is triggered by the rising edge and falling edge of the SIN signal after a short time delay (tPD_XN). XP signal has a 700ns pulse-width and is triggered by the rising edge of the SOUT signal after an adjustable time delay (tDLY_XP) and by the falling edge of the DET signal. The relation between the delay resistor (RDELAY) and the delay time is shown in Figure 17. The triggering of the XP signal by DET is prohibited while the XN signal is HIGH. Therefore, the XP signal is not triggered at the falling edge of the DET signal and is delayed until the XN signal drops to zero at heavy-load condition. At light-load condition, the DET falling edge comes after the XN signal drops to zero and the XP signal is triggered at the falling edge of the DET signal after a short time delay (tPD_DET).
Vgs Q1,Q2 Vx Vin
VD Vin IM
IL
ID1
ID2
Figure 14. Key Waveforms of Dual-Forward Converter
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter
Heavy load condition
SIN SOUT XP
50ns 300ns Programmable delay 700ns 100ns 50ns 700ns 300ns
Programmable delay 50ns
XN
300ns
50ns
300ns
300ns
Gate drive for Powering SR
Gate drive for Free-wheeling SR
DET
Light load condition
SIN SOUT XP
50ns 300ns Programmable delay 700ns 100ns 50ns 700ns Programmable delay 50ns 50ns 300ns 300ns 300ns
XN
300ns
Gate drive for Powering SR
Gate drive for Free-wheeling SR
DET
Figure 16. Timing Diagram
t DLY_XP (ns)
350 300 250 200 150 100
Under-Voltage Lockout (UVLO) The power-on and -off threshold of FAN6210 are fixed at 10V and 8V, respectively. The VDD pin can be connected with the power source of the PWM controller. VDD Pin Over-Voltage Protection VDD over-voltage protection prevents damage due to abnormal conditions. Once the VDD voltage exceeds the VDD over-voltage protection voltage (VDD-OVP) and lasts for tOVP, FAN6210 stops operation. Green-Mode Operation
5
7.5
10
12.5 15
17.5
20
22.5
25
RRDLY (k)
Figure 17. Programmable Delay with Resistor
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
To improve light-load efficiency, green-mode operation is employed, which disables the SR turn-on trigger signal, minimizing gate drive power consumption at light-load condition. Green mode is enabled when the duty cycle of SIN is smaller than 10%.
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger for Dual Forward Converter
Typical Application Circuit (Dual-Forward Converter with SR)
Application Fairchild Devices
FAN480X PC Power FAN6210 FSR660 FSR630 90~264VAC 12V/16.5A 5V/18A
Input Voltage Range
Output
VIN VAC PFC stage
FCP20N60 UF1007 4.7 (primary 300H) 1:1.2 100F 10k 56H 1.8H
VO=12V
1N4148
74:7
110k
1 DET GND 2
6
3
LPC VDD
2200F 2200F
10k
10k
4.7 10k 1:1.2 1N4148 FR107 FCP20N60 UF1007 10k
SN 5
SP 4
DET 1 5 SN 4 SP
GND 2 LPC 6 VDD 3
10k
FSR660
IPWM (To FAN480X)
470pF
470
FSR660
11H 2H
VO=5V
0.15 10 74:3 20k
1 DET GND 2
6
3
1 XP
10
GND 8 SOUT 7 VDD 6
5.1k 10k ZD/5.6V
LPC VDD
330F 220F
2 XN 3 SIN
8.2k
OPWM (From FAN480X)
1N4148
SN 5
SP 4
4 RDLY DET 5
DET From VDD of FAN480X
1N4148
1 5 SN 4 SP
GND 2 LPC 6 VDD 3
10k
FSR630
FAN6210
1N4148
12V
5V
1N4148
1N4148
1:1 (160H)
FSR630
3k 30k PC817 1k 1F 15k
TL431 5.1k
Figure 18. Application Circuit
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger for Dual Forward Converter
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 19. 8-Pin Small Out-Line Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
10
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(c) 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1
11
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FAN6210 -- Primary-Side Synchronous Rectifier (SR) Trigger for Dual Forward Converter

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